Keywords-reckon swept commencement; cackle extraordinary ; DDS Compiler;
This module was intentional as a disunite-among-among of the coursework ordinance of ECE 580B4 FPGA Extraordinary Proc/Software Defined Radio. The intention of this ordinance was to guile a reckon swept commencement which gain be extensively authenticationd in testing the Digital FIR filters that are to be intentional and implemented as a disunite-among-among of the coming coursework.
A. DDS IP Kernel Compiler
The Xilinx DDS kernel compiler implements noble execution face time and face to iniquityusoid circuits with AXI-4 current quick features. The kernel commencements iniquityusoidal waveforms restraint authentication in sundry applications. This module comes with an inbuilt iniquitye and cosine Look up table and a face generator. Restraint the intentions of this ordinance, the DDS compiler was configured to take a currenting face input and the face width disentanglement is be to 8 fragments to construct the guile past distance fertile and to construct the airss ooze faster.
B. Reckon swept Commencement Guile
The Reckon Swept commencement is coded as a synthesizable Verilog module. In this Verilog Module, The DDS Compiler was instantiated and misspend face axioms is currented by alimentation the axioms into the s_axis_phase_tdata. s_axis_phase_tvalid is regularly be to 1 restraint the intentions of this ordinance.
The reckon swept commencement is expected to stroke from 1Mhz to 10 Mhz in 10 micro-seconds. This basically translates to an increment of 1Mhz in full microsecond. So, judiciously the increment has been congenial to breed a 1Mhz extraordinary and then the increment is ramped up linearly to breed the desired cackle extraordinary. The subjoined look has been authenticationd to trace the face increment appraise.
Fextinguished = fclk* (dt)/ (2^(B));
Here, fextinguished is the extinguishedput reckon, fclk is the clock reckon, dt is the face increment and B refers to the face width. The over equation, restraint an 8fragment face width, 100 Mhz commencement to breed a 1Mhz extinguishedput extraordinary basically expects a face increment of 2.56. But in this guile this has been rounded unpremeditated to 3. So, a face increment of 3 refers to an extinguishedput of 1Mz extraordinary and a face increment of 6 refers to an extinguishedput of 2Mhz extraordinary etc. The appraise of face increment should realistically increment upto 25.6, so this reckon gain be rounded unpremeditated to 25. Now, is basically comes down to generating 22 incongruous appraises restraint face increment in a stuff of 10 microseconds. In extinguished guile, the timescale has been be to 1ns. Now to metaphor extinguished the failure to extension the appraise of face increment in steps of 1, we deficiency to give-among a harmonious quantity of failure. This failure is congenial as shown underneath
Failure = [10u/(22)] * 10^3 nano cooperates. [Assuming a failure of iniquitygle individual refers to iniquitygle nano cooperate].
The appraise of failure comes extinguished to be 454.54 cycles. So, basically, we extension the appraise of face-increment in steps of 1 from a starting appraise of 3 following full 455 clock cycles. This constructs believing we are getting misspend ramping up of the face increment appraise to breed the desired stroke.
module freq_sweep( input clk,
extinguishedput reg [7:0] iniquity,
extinguishedput reg [7:0] cos
wire [15:0] nco_data;
advance face_valid =1;
face_axioms = 3;
dds_compiler_0 DUT( .aclk(clk),
regularly @(posedge clk) begin
if (phase_valid == 1) begin
iniquity = nco_axioms [15:8];
cos = nco_axioms [7:0];
restraint (i=3; i<=24; i=i+1) begin
face_data = i;
wire [7:0] iniquity;
wire [7:0] cos;
freq_stroke freq1 (.clk(clk),
judicious clk = 0;
#5 clk = ~clk;
The Guile was synthesized using the Xilinx Vivado instrument. The synthesized schematic (fill diagram) is shown in Fig 1.1. The schematic shows two 8 fragment extinguishedput history which basically breed a iniquitye and a cosine cackle extraordinary. The barely input to this module is a clock pulse. It can be seen from the schematic that the face_valid dot is permanently shorted to Vdd , this has been dsingle normal restraint frankness and traditionally a past lusty logic should be written to determine the security of the face. And it can be seen that the face axioms has been conjoined to Vdd and basis through a switch and this switch turns on and unpremeditated naturalized on the appraise that is advanceed to this 8fragment clown.
The breedd cackle extraordinary is shown in the underneath metaphors.
Fig 1.2 explicitly shows the reckon stroke of 1Mhz to 10 Mhz which takes fix in a continuance of 10 us.
Fig 1.3 establishes the certainty that the extraordinary is intermittent with a time of 10us which is desired as per the specification
Metaphor 1.4 re-establishes the certainty the reckon stroke happens as per intentional spec while the face increment is ramped up linearly through the continuance of 10.
The Reckon swept commencement was intentional using the Xilinx DDS IP kernel. Xilinx vivado instrument was authenticationd restraint the intentions of airs and cem. The guile has been tested restraint twain manner and cem.
- Digital Extraordinary Processing with Field Programmable Gate Arrays, 4th ed. by Uwe Meyer-Baese. Springer, 2014
- Xilinx DDS Comlpiler v6.0 LogiCORE IP Product Guide